1. Field of the Invention
The present invention relates to a method and apparatus for driving a plurality of buses in a high speed microprocessor.
2. Discussion of the Related Art
Performance of microprocessors employing buses with a pipeline structure may require a data by-pass implementation for the buses. The number of by-pass buses may increase as the size of the pipeline becomes greater. When loading the same data for a multiplicity of buses, each bus may request another bus driver in parallel. Accordingly, when a bus driver is requested, corresponding to the number of buses, there may be an increase in the amount of a control signals required to operate the buses.
Some examples of buses with a pipeline structure include e a single-rail bus structure and a dual-rail bus structure. In the single rail bus structure, substantial time may be required for charging and discharging data buses, because of a large swing width between high and low voltage levels. As a result, there is a reduction in the performance of the microprocessors, caused by inducing, in order to increase power consumption. In contrast, the dual-rail bus structure may have a fast response speed with low power, due to a narrow swing width, when compared to the single-rail bus structure.
FIG. 1 is a block diagram showing a bus driver of a conventional 32-bit microprocessor having a triple dual-rail bus structure. Referring to FIG. 1, the conventional bus driver includes a byte rotator 102, a buffer circuit 104 and sign extenders 106, 108 and 110. The byte rotator 102 divides the 32-bit data received from a data source into 4 bytes. The byte rotator 102 changes the position of each byte, according to a byte-operation, to output rotated data (Data_R). The sign extenders 106, 108 and 110 convert the rotated data, not selected by the byte-operation, into a sign value according to the byte-operation. Additionally, the sign extenders 106, 108 and 110 are a part of each individual bus (a first bus, a second bus and a third bus) respectively. As not shown in FIG. 1, the conventional sign extenders 106, 108 and 100 may use NMOS-2 stacks of transistors (N1 and N2 respectively) as a final bus driver.
As shown in FIG. 1, to load data to several buses (the first, second and third buses), it is essential for a conventional bus driver to have sign extenders 106, 108 and 110, including a bus driver, which may be implemented by the NMOS-2 stack at each bus. As a result, the capacity of a gate capacitor of the byte rotator 102 and a metal capacitor is increased.
Integrated and high-performance microprocessors have previously required several buses. As a result, since the number of bus driver circuits are increased, and corresponding buffers are added, the dimension component of the hardware is increased. Therefore, the control logic becomes more complex, and the performance of the microprocessors is reduced.